See the pins of a running FPGA. No rebuild.
ChipJTAG Omni reads the boundary-scan cells over JTAG while your design runs and draws each pin as a waveform. Nothing is added to the design, and capturing never drives a pin.
Features
Bring-up and debug from the pins you already have
Pick pins from the device's BSDL, give them your signal names, and watch power, reset and status lines while the board runs its real firmware.
Live pin waveforms
Sample every boundary-scan cell in the chain and draw the pins you choose as waveforms, with your own names from a pin map.
Recording and export
Save sessions as .CJ files and export VCD or CSV for your simulator, scripts or test reports.
Waveform Compare
Line up a simulation VCD with a hardware capture and find where the board departs from the model.
Agent MCP
Let an AI agent run the capture, wait for conditions and check timing over the Model Context Protocol. ChipJTAG Omni computes every verdict.
Serial terminal
A USB-UART terminal beside the waveforms, so console output and pin activity line up in one window.
CPU and MCU Debug
Read the DE1-SoC HPS debug port read-only, or core state and memory through probe-rs debug probes. Their agent tools come with Agent MCP.
How it works
Three steps to the first waveform
Connect the cable
Use an FTDI-based JTAG cable, an Intel USB-Blaster or an AMD/Xilinx cable through Vivado's hardware server.
Load the BSDL and pin names
Point ChipJTAG Omni at the device's BSDL file. Import a Lattice
.lpfor a saved configuration to see your own signal names.Capture, compare, automate
Watch the pins live, record the run, compare it with simulation, or hand the session to an AI agent.
Agent MCP
Your AI agent runs the measurement
Agent MCP connects ChipJTAG Omni to AI coding agents that speak the Model Context Protocol. The agent asks for a capture and a timing check; ChipJTAG Omni measures and returns the verdict, so the numbers never come from the language model.
- Timing checks: delay, order, quiet time, pulse width and period.
- Wait for a pin condition, then capture.
- Edge lists and reports that cite the recording.
agent › capture pins=PWRGD_3V3,RST_N until=RST_N↑ omni ‹ recorded 42.00 ms, 2 pins, 3 edges agent › check_timing delay PWRGD_3V3↑ → RST_N↑ min=10 ms omni ‹ PASS Δt = 12.40 ms (edges at 9.50 ms, 21.90 ms)
Example session, simplified. Tool names and arguments differ in the real protocol.
Ordering information
One price list, every paid feature in each plan
Plans differ only in how many computers can use the license at the same time.
| Plan | Computers | Price | Order |
|---|---|---|---|
| Standard | 1 | US$99 / year | Buy |
| Personal | 2 | US$149 / year | Buy |
| Team | 5 | US$349 / year | Buy |
- Every plan includes recording and export, Waveform Compare, Agent MCP, and terminal logging and macros.
- Annual subscription that renews automatically. Cancel at any time; the license runs to the end of the paid year.
- Refunds within 14 days of a purchase or renewal. See the Refund Policy.
- Prices in US dollars. Sales tax or VAT is calculated at checkout for your location.
- Our order process is conducted by our online reseller Paddle.com. Paddle.com is the Merchant of Record for all our orders.
What stays free after the trial
The 30-day trial starts on first launch and includes every paid feature.
| Feature | Free | Trial | Paid |
|---|---|---|---|
| Live waveforms and snapshots | Yes | Yes | Yes |
| Serial terminal | Yes | Yes | Yes |
| CPU and MCU Debug (alpha) | Yes | Yes | Yes |
| Save recordings, export VCD and CSV | No | Yes | Yes |
| Terminal logging and macros | No | Yes | Yes |
| Waveform Compare | No | Yes | Yes |
| Agent MCP | No | Yes | Yes |
Operating conditions
Requirements
- Windows 10 or 11, 64-bit (x64).
- FTDI-based cables: FTDI's D2XX driver. Windows Update usually installs it when the cable is first plugged in.
- Intel USB-Blaster and USB-Blaster II: the cable driver and Quartus Programmer.
- AMD/Xilinx cables: Vivado or Vivado Lab with its hardware server.
- A BSDL file for each device in the chain, from the device vendor.
- Internet to activate a license, then at least once every 30 days.
Limits
What it is built for
- Slow control and status signals. Boundary-scan sampling reaches about 50–100 µs per sample at best. That suits power sequencing, resets, straps, enables, interrupts and LEDs, not clocks or data buses.
- Not a replacement for an on-chip logic analyzer. For fast signals, use the vendor's embedded analyzer.
- Check your cable and board first. Compatibility with every cable, device and board is not claimed. Use a test board and a known-good BSDL.
Questions
FAQ
Does ChipJTAG Omni change my FPGA design?
No. It reads the boundary-scan cells through the JTAG port while the design runs. There is no IP core to add and nothing to recompile.
What happens when the 30-day trial ends?
Live waveforms, snapshots, the serial terminal and the CPU and MCU Debug extensions stay free. Saving and exporting recordings, Waveform Compare, Agent MCP, and terminal logging and macros need a plan.
Can I move my license to another computer?
Yes. Activate on the new computer with your purchase email and the code we send to it. When every seat is in use, you can replace one computer, once every 30 days per email address. Write to support if you need an exception.
Does it need an internet connection?
Only to activate, and then at least once every 30 days so the license renews itself. Captures, recordings and project files stay on your computer.
How do I cancel?
Use the subscription link in your Paddle receipt email, or write to support. The license keeps working until the end of the year you paid for.
Who handles payment, tax and invoices?
Paddle.com, our reseller and Merchant of Record. Paddle charges your card, adds sales tax or VAT where it applies, and emails the receipt.
Download ChipJTAG Omni 1.0.0
The 30-day trial starts on first launch. Buy or activate a license later in Settings, under License.